1. Field of Invention
The present invention relates to a memory and manufacturing method thereof. More particularly, the present invention relates to a non-volatile memory and manufacturing method thereof.
2. Description of Related Art
In various non-volatile memory products, as the electrically erasable programmable read-only memory (EEPROM) can perform multiple times of operations of programming, reading, erasing, etc. and has the advantage that the saved data will not be lost after the power is off, it has been a memory unit widely applied in personal computer (PC) and electronic devices.
The typical EEPROM includes a floating gate and a control gate made of doped polysilicon. In order to avoid the data error due to the seriously excessive erasing/writing when the typical EEPROM performs erasing/writing operation, a select transistor is connected in serial at one side of the control gate and the floating gate so as to form a two-transistor (2T) structure. The select transistor can control the programming and reading of the memory.
Referring to U.S. patent application No. US 2004/0183124 A1, the patent application provides a flash memory cell, wherein a select gate is disposed in the substrate so as to reduce the device size of the flash memory cell and improve the device integration.
Although the memory can reduce the width size of the memory, the channel length of the memory may be shortened accordingly. Therefore, when operating the non-volatile memory with 2T structure, the leakage current may cause program disturbance etc. in different bias voltage, so that the memory is written wrongly.
The above problem may reduce the reliability of the memory and cause poor efficiency of the product. It can be learned that by increasing the channel length and reducing the leakage current while keeping the device integration is an immediate problem to be resolved.